The present invention is directed to computer aided circuit design and, more particularly, to a method and system for automatically abutting p-cell layouts based on position and orientation of abutting instances.
In circuit design, a parameterized cell (p-cell) is a cell that is automatically generated by an electronic design automation (EDA) tool based on a value or values of governing parameters. That is, a p-cell represents a part or a component of a circuit that is dependent on one or more parameters, such as transistors or the like.
Analog and memory circuit designs typically require abutting p-cell instances having different dimensions. These designs cause design rule check (DRC) errors due to the limitations of the abutment functionality in current EDA tools, and there currently is no control at the p-cell code level to resolve such issues. The solution offered by current EDA tools for auto-abutment is placement of a stopping gate at 40 nm and lower technologies. In one conventional automatic abutment procedure, the EDA tool considers the overlap of pins in the first and second instances, and automatically adjusts the pin arrangement in the abutted configuration to remove redundant pins. However, this tool does not take into account the position and orientations of the respective instances, and therefore does not alter other necessary parameters to avoid the types of DRC errors described above.
It is therefore desirable to provide a method for an EDA tool to make alterations to components of abutting p-cells that avoid the types of DRC errors caused by the automatic abutment of two differing p-cells.